Design of an ultra-low-power active-electrode system for wearable ECG acquisition

Name: Techapon Songthawornpong

LCSH: Kasetsart University -- Dissertations. D.Eng. (Electrical Engineering) 2024

Classification :.LCCS: RC683.5.E5

LCSH: Kasetsart University. -- Department of Electrical Engineering -- Dissertations

LCSH: Electrocardiographs

LCSH: Electrocardiography

LCSH: Electronics in cardiology

LCSH: Signal processing

LCSH: Electronic circuits

LCSH: Biomedical engineering

Abstract: This research presents the design of a low-power active-electrode (AE) system for multi-lead ECG acquisition. The whole system comprises two AEs for sensing ECG from dry electrodes, a digital driven-right-leg (DRL) circuit for suppressing powerline interference on the patient’s body to improve the commonmode rejection ratio (CMRR) of the system, and a backend processing circuit for signal conditioning and digitization of the ECG signals. The main focus of the design is to develop a discrete-time equivalent model for optimizing the digital DRL circuit in terms of stability, complexity, CMRR improvement, and power usage. Our design concept was validated through a functional prototype of the proposed system built using commercially available components. The AE system achieves an exceptional CMRR of 115.86 dB with a 77.6-dB enhancement due to the DRL circuit. Even with only 6-bit data converters with a 3.3-V full-scale range used in the DRL circuit, the AE pair, exhibiting a low intrinsic CMRR of 38.26 dB, can record ECG with negligible quantization noise and powerline interference. As part of this thesis, I describe the design of a compact low-power motion-artifact (MA) estimator and a low-noise fully-differential bandgap reference (BGR). The estimator employs a mixed-signal architecture that performs adaptive filtering on the electrode impedance information to derive a cancellation signal to suppress the MA at the ECG acquisition system’s input. Fabricated in a 0.18-μm CMOS process, the estimator occupies an active area of 0.11 mm2 and consumes 2.6-3.2 μW of power from a 1-V supply. The low power consumption and small area make the estimator suitable for local placement at each recording channel in multi-channel ECG acquisition systems. For the BGR, the design prioritizes low output noise and high load-driving capability to ensure compatibility with highprecision data converters. Noise minimization is achieved by carefully optimizing various devices and bias currents, while loop bandwidth is maximized for a given bias current to drive load efficiently. Designed with 3.3-V devices in a 0.13-μm CMOS process, the BGR occupies an active area of 0.2 mm2 and consumes 62 μA from a 3.3-V supply while providing a reference voltage of 2.048 V. The BGR achieves an excellent integrated noise of 13.6 μVrms from 0.1 Hz to 200 Hz

Kasetsart University. Office of the University Library

Address: Bangkok

Email: tdckulib@ku.ac.th

Name: Woradorn Wattanapanitch

Role: Thesis Advisor

Created: 2024

Modified: 2026-06-15

Issued: 2026-06-15

วิทยานิพนธ์/Thesis

วิทยานิพนธ์/Thesis

application/pdf

URL: https://kasetsart.idm.oclc.org/login?url=https://www.lib.ku.ac.th/KUthesis/2567/techapon-song-all.pdf

CallNumber: RC683.5.E5.T43

eng

DegreeName: Doctor of Engineering

Level: Doctoral Degree

Descipline: Electrical Engineering

Grantor: Kasetsart University

©copyrights Kasetsart University

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