แจ้งเอกสารไม่ครบถ้วน, ไม่ตรงกับชื่อเรื่อง หรือมีข้อผิดพลาดเกี่ยวกับเอกสาร ติดต่อที่นี่ ==>
หากไม่มีอีเมลผู้รับให้กรอก thailis-noc@uni.net.th
หากไม่มีอีเมลผู้รับให้กรอก thailis-noc@uni.net.th
Phichet Moungnoul. Evaluation of multi-bit input logic blocks in RTL designed FPGA architecture : a framework for FPGA and ASIC integration. (). King Mongkut's University of Technology North Bangkok. Central Library. : , 2025.
Evaluation of multi-bit input logic blocks in RTL designed FPGA architecture : a framework for FPGA and ASIC integration
Name: Sato, Tomoaki
Organization :
Hokusei Gakuen University. Dept. of Management Information
Email :
t-sato@hokusei.ac.jp
Name: Murakami, Anyu
Organization :
Hokusei Gakuen University. Dept. of Management Information
Email :
i21059@hokusei.ac.jp
Name: Sorawat Chivapreecha
Organization :
King Mongkut's Institute of Technology Ladkrabang. School of Engineering
Email :
sorawat.ch@kmitl.ac.th
Name: Phichet Moungnoul
Organization :
King Mongkut's Institute of Technology Ladkrabang. School of Engineering
Email :
phichet.mo@kmitl.ac.th
keyword:
Hardware-software integration
LCSH:
Logic design
Abstract:
This paper explores the evaluation and optimization
of multi-bit input logic blocks (LBs) within RTL-designed FPGA
architectures. Traditional FPGA designs face limitations in power
consumption, delay, and area due to the constraints of
reconfigurable circuits. The proposed architecture leverages RTLlevel
design capabilities to address these challenges and enables the
co-design of FPGAs and ASICs. The authors evaluate the
performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay,
area, and synthesis feasibility. The results demonstrate that 8-bit
input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm²,
outperforming multi-stage smaller LBs. Although 16-bit input LBs
show potential for delay reduction, their synthesis demands
significant time and results in a large area footprint, rendering them
impractical. Synthesis of 32-bit input LBs was not feasible due to
current tool limitations. These findings highlight the effectiveness
of 8-bit input LBs for pattern matching tasks and emphasize the
importance of application-specific optimization. The fixed routing
feature of RTL-designed FPGAs facilitates the development of
efficient, customizable designs tailored to specific workloads. This
work contributes to the advancement of FPGA architectures,
offering insights for future research on larger input LBs and their
integration into high-performance applications.
King Mongkut's University of Technology North Bangkok. Central Library
Address:
BANGKOK
Email:
library@kmutnb.ac.th
Created:
2025
Modified:
2025-06-26
Issued:
2025-06-26
บทความ/Article
application/pdf
BibliograpyCitation :
In Electrical Engineering Academic Association (Thailand) and King Mongkut's University of Technology North Bangkok. Department of Electrical and Computer Engineering. 13th International Electrical Engineering Congress (iEECON 2025) (P06483). Bangkok : Electrical Engineering Academic Association (Thailand), 2025
eng
©copyrights King Mongkut's University of Technology North Bangkok
RightsAccess:
ใช้เวลา
0.042441 วินาที
Sato, Tomoaki
| Title | Contributor | Type |
|---|---|---|
| Optimal number of wires for circuits on RTLDesigned FPGAs
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Sato, Tomoaki;Hayashihara, Yuya;Yokota, Shione;Sorawat Chivapreecha;Phichet Moungnoul | บทความ/Article | |
| Evaluation of multi-bit input logic blocks in RTL designed FPGA architecture : a framework for FPGA and ASIC integration
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Sato, Tomoaki;Murakami, Anyu;Sorawat Chivapreecha;Phichet Moungnoul | บทความ/Article |
Murakami, Anyu
| Title | Contributor | Type |
|---|---|---|
| Evaluation of multi-bit input logic blocks in RTL designed FPGA architecture : a framework for FPGA and ASIC integration
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Sato, Tomoaki;Murakami, Anyu;Sorawat Chivapreecha;Phichet Moungnoul | บทความ/Article |
Sorawat Chivapreecha
| Title | Contributor | Type |
|---|---|---|
| Optimal number of wires for circuits on RTLDesigned FPGAs
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Sato, Tomoaki;Hayashihara, Yuya;Yokota, Shione;Sorawat Chivapreecha;Phichet Moungnoul | บทความ/Article | |
| Evaluation of multi-bit input logic blocks in RTL designed FPGA architecture : a framework for FPGA and ASIC integration
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Sato, Tomoaki;Murakami, Anyu;Sorawat Chivapreecha;Phichet Moungnoul | บทความ/Article |
Phichet Moungnoul
| Title | Contributor | Type |
|---|---|---|
| Optimal number of wires for circuits on RTLDesigned FPGAs
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Sato, Tomoaki;Hayashihara, Yuya;Yokota, Shione;Sorawat Chivapreecha;Phichet Moungnoul | บทความ/Article | |
| Evaluation of multi-bit input logic blocks in RTL designed FPGA architecture : a framework for FPGA and ASIC integration
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Sato, Tomoaki;Murakami, Anyu;Sorawat Chivapreecha;Phichet Moungnoul | บทความ/Article |